Tessera Reveals Ultra-Thin Wafer-Level CSP December 18, 2006
Intended to trim down image sensors and other optical devices, SHELLCASE RT debuts as one of the thinnest, wafer-level chip scale packaging (WLCSP) technologies to date. Thickness is reported as 0.5 mm. Built on the company’s foundational wafer-level encapsulation technology, SHELLCASE RT forecasts high yields by protecting components from contamination that may occur in the initial stage of packaging. In addition, the platform’s enhanced reliability predicts emerging opportunities in the realm of cameras for use in harsh environments and automotive electronics. Other features include full compatibility with conventional chip-on-board processes, compliance with JEDEC MSL 1 reliability standards, and support for narrow scribe lines down to 100 µm as well as smaller and finer-pitch bond pads. The company is currently licensing the technology to interested parties. For more details, call TESSERA INC., San Jose, CA. (408) 894-0700.
