Altera Launches High-End Stratix FPGAs November 08, 2006
Reporting 50% lower power consumption, 25% higher performance, and twice the density of Stratix II devices, the Stratix III FPGA family employs TSMC’s 65-nm process and features hardware architecture advancements and Quartus II software enhancements. Reductions in power consumption are attributed to the company’s programmable-power technology, which maximizes performance where needed while lowering power elsewhere in the design. The technology allows each programmable logic array, DSP, and memory blocks to operate independently at high speed or low power. The PowerPlay feature in Quartus II software version 6.1 automatically analyzes a design and identifies which blocks require the highest performance, setting these to high-speed mode. All other logic is automatically put into low-power mode. Another power feature, selectable core voltage, provides options to select either 1.1V for demanding designs or 0.9V for minimal requirements. The FPGAs support over 40 I/O interface standards and their memory interfaces employ programmable I/O delay, drive strength, slew rate, read/write leveling, and 31 embedded registers per I/O for maximum DDR3 performance. In terms of memory, Stratix III TriMatrix memory includes three block sizes: MLAB blocks, M9K blocks, and M144K blocks. The M144K blocks are said to enable higher memory bandwidth than any other FPGA memory architecture and up to 17 Mb of memory performing at 600 MHz. Additionally, Stratix III devices lay claim to being the only FPGAs with support for the 256-bit Advanced Encryption Standard (AES). Engineering samples of the first Stratix III device will be available in the third quarter of 2007. Pricing starts at $549 each/1,000. ALTERA CORP., San Jose, CA. (408) 544-7000.
