CEVA’s Quad-MAC DSP Eyes Next Gen Multimedia January 2007 Issue Published Date: October 31, 2006
Joining the CEVA-X DSP family of cores and compliant with the CEVA-X instruction set architecture, the CEVA-X1641 is the family's first quad-MAC DSP core and is designed to run computational intensive tasks that require substantial data throughput and high memory bandwidth. The core is fully synthesizable via its enhanced memory architecture. Like its siblings, the core combines a VLIW/SIMD architecture with features to handle 4G technologies and multimedia applications. Main features include four MAC units operating in parallel, 8-issue VLIW, 24 40-bit accumulators, a 128-bit data bandwidth, 8-/16-/32-/40-bit data operands and operations, and 16-/32-bit instructions. The CEVA-X1641 with a complete software-development tool chain is available now for licensing. CEVA INC., San Jose, CA. (408) 514-2900.
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