New App From The Mathworks Generates HDL Code From System Models September 21, 2006
[September 18, 2006] The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces target-independent Verilog and VHDL code and test benches for implementing and verifying ASICs and FPGAs. Generated code is both bit-true and cycle-accurate, derived from 80 standard blocks in Simulink and Signal Processing Blockset, as well as Mealy and Moore finite-state machines in Stateflow. Additionally, the code works with established hardware implementation and verification tools. Legacy HDL code and third-party HDL intellectual property can also be verified with Simulink models and integrated with the code that is automatically generated by the HDL Coder. Available for Windows, UNIX, and Linux platforms, list prices start at $15,000. THE MATHWORKS, Natick, MA. (508) 647-7000.
