Structured ASICs Embed PCI Express PHY November 2005 Issue Published Date: November 04, 2005
Fabricated with an eight-metal, 0.13-µm process, the CX6100 family of structured ASICs integrates a PCIe PHY that is compliant with the current 1.1 version of the specification. In addition to the embedded PHY, the devices offer an optional PCIe-compliant controller. Using the optional controller, users can quickly develop root port, bridge, and endpoint designs. The controller supports one, four, or eight lanes, up to eight VCs, and up to six BARs. It features configurable retry buffers and support for up to 4-KB payloads. The controller comes with simulation models, driver software examples, and all documentation. Twelve devices in the family offer densities ranging from 240K to 1.8M ASIC gates, up to 1.1 Mb of SRAM, and maximum operating frequencies up to 250 MHz. Four configurable PLLs support output frequencies from 10 MHz to 1 GHz. Pricing starts below $7 each/100,000. CHIPX, Santa Clara, CA. (800) 952-4479
