Device Supports ARM9 Multi-CPU Evaluations May 2004 Issue Published Date: May 03, 2004
The MB87Q1100 ARM9 multi-CPU evaluation device integrates the ARM926EJ-S and ARM946E-S macrocell cores in the company’s next-generation SoC platform. The platform adopts multi-CPU capabilities and its unique, multi-layer high-performance bus (AHB) reduces power consumption to a typical 450 mW at a CPU speed of 200 MHz. It also employs the external extension function of AHB-Lite, a subset of the AHB bus, allowing users to design and verify modules in their ASICs by connecting the master and slave module of AHB-Lite to the device. Other features include a flash and SDRAM memory controller, eight-channel DMA controller, interrupt controller, two-channel UART, 2 x 2-channel timer, GPIO interface, and power-saving features. Available in a 400-pin FBGA, price is $230 each/1,000. For more information, contact Emi Igarashi at FUJITSU MICROELECTRONICS AMERICA, INC., Sunnyvale, CA. (408) 922-9104.
