SoC Integrates ASIC And FPGA Technologies January 2004 Issue Published Date: January 13, 2004
By integrating both ASIC and FPGA technologies, the ORSP14 field-programmable system-on-chip (SoC) is said to be a higher performance and lower power SPI4.2 device compared to a full FPGA deployment. The chip's ASIC block includes two SPI4.2 interface blocks, a QDRII SRAM controller, four channels of 600 Mb/s to 3.7 Gb/s Serdes 8b/10b encoding and decoding, and other support logic. An FPGA is connected to the ASIC block that contains greater than 16,000 logic elements and embedded RAM. The SPI3.4 cores provide dual 10-Gb/s physical-to-link interfaces, and each block provides a bi-directional interface with an aggregate bandwidth of 14.4 Gb/s. To provide wire-speed packet processing, the device employs an independent memory controller block that buffers data between the FPGA logic and external memory. This block supports throughput rates in excess of 20 Gb/s. Other features of the SoC include a microprocessor interface, 32-bit internal system bus, and integrated system registers. Available in a 1-mm ball pitch, thermally-enhanced FPBGA, ORSP14 costs $250 each/10K. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.
