RISC Controller Grooms For Low-Cost Networking Apps June 2003 Issue Published Date: June 01, 2003
Focussing on cost-sensitive networking and consumer convergence applications, the T6TC1XB-0001 ARM-based RISC networking controller is the first device in the company's SoCMosaic line of system-on-chips (SoCs). Constructed using an ARMv5TEJ RISC architecture and integrating a 150 MHz ARM926EJ-S CPU with 16 KB of instruction and data caches, the controller is usable either as is or as a template to design custom chips with a six-month turnaround time. The device packs two Ethernet MAC ports and a PCI controller that can perform as a host bridge controller or as a multi-function PCI adapter. Operating on 3.3V and a 1.5V internal core voltage, power dissipation at 150 MHz is 500 mW. Other features include DSP instruction extensions, ARM Jazelle technology with Java byte-code acceleration, a distributed DMA architecture that gives each device its own DMA, and 8 KB of local scratch pad SRAM. The controller also integrates a SDRAM controller that accommodates up to two banks of SDRAM, with up to four banks possible via interleaving. Samples in a 352-bump PBGA will be available in July with production expected in the third quarter. Sample pricing is $14.25 each/1,000. For further information, call TOSHIBA AMERICA ELECTRONIC COMPONENTS INC., San Jose, CA. (408) 526-2400.
