Network SRAM Features Ultra-Wide 72-Bit Bus March 2003 Issue Published Date: March 01, 2003
The 18 Mb SigmaRAM network SRAM operates at a 350 MHz clock speed over a 72-bit bus width and has a data throughput rate of 25 Gb/s. The device employs an architecture with an open set of standards that allows memory scaling using the same package—users can deploy an 18 Mb device, for example, and then replace it later with a 36-, 72-, or 144-Mb device without redesign. The 350 MHz SigmaRAM is available in both 72-bit wide (M5M5Y5672TG) and 36-bit wide (M5M5Y5636TG) configurations, operating with a 1.8V power supply. It conforms to the SigmaRAM Consortium’s 1x1Dp double-late-write, pipeline-read specification. Devices meeting the SigmaRAM 1x1Lp late-write, pipeline-read specification are also available in both 72-bit-wide (M5M5Y5972TG) and 36-bit-wide (M5M5Y5936TG) configurations. Housed in a 209-ball BGA package measuring 14 mm x 22 mm with a 1-mm ball pitch, pricing for the M5M5Y5672TG device is $100 each in sample quantities. MITSUBISHI ELECTRIC & ELECTRONICS USA, INC., Sunnyvale, CA. (408) 774-3189.
