Performance Boosted And Security Features Added To FPGA Family October 2002 Issue Published Date: October 01, 2002
The ProASIC Plus field-programmable gate array (FPGA) family has been expanded to include the APA075, a 1-million system gates FPGA. Additionally, the device integrates the company's FlashLock on-chip security feature that promises levels of design security beyond conventional SRAM-based FPGAs and ASICs. The device is user programmed with a key ranging from 79 to 263 bits that blocks external attempts to read or alter the configuration settings—via FlashLock, users can lock the design after programming to prevent unauthorized changes. Related design software has also been enhanced. Improvements to the Quadratic Placer in Designer R1-2002 software and the inclusion of place-and-route, timing analysis and memory generation functionality in the Libero integrated design are said to deliver a 20% performance boost. Other features of the APA075 include system speeds of up to 100 MHz, two advanced clock-conditioning blocks, and two LVPECL differential input pairs. In-system programmability (ISP) is supported through the IEEE standard 1149.1 JTAG interface. The APA075 is priced below $8 each/100K. More details are available from ACTEL CORP., Sunnyvale, CA. (888) 992-2835.
