Clock Generator Employs Digital PLL Control August 2002 Issue Published Date: August 01, 2002
The SCG6500NT synchronous clock generator is a LVPECL low-jitter, high-precision, phase-lock-loop frequency translator. According to the company, this clock generator provides designers with the reliability they need to optimize the performance of their telecom network equipment. It provides the following LVPECL differential outputs: 622.08 MHz (_0.8 ps jitter); 155.52 MHz (_1 ps jitter); two 77.76 MHz (_4 ps jitter); and 8 kHz. Switching between reference input signals can be achieved either manually or autonomously. Modules in the SCG6500NT series are said to be well suited for OC-48/OC-192 line cards, SERDES, and service termination cards to add synchronization for TDM, PHD, SONET, and SDH network equipment. The SCG6500NT operates with a 3.3 Vdc power supply. CONNOR-WINFIELD CORP., Aurora, IL. (630) 851-4722.
