Through use of its patent-pending Virtex-II IP Immersion technology, the company says it has managed to meld on a single chip all of the ingredients needed to achieve end-to-end connectivity for next generation programmable datacomm systems. Called the Virtex-II Pro FPGA family and made using IBMÕs advanced 0.13-micron, 9-layer copper process, the new devices integrate on-chip up to four embedded RISC PowerPC processors and up to 16 RocketIO 3.125-Gbps serial transceivers, with the new FPGAs supporting both existing parallel interface standards, such as POS PHY Level 4 and Flexbus 4, as well as emerging serial standards, such as 3GIO, InfiniBand and Serial RapidIO. The Virtex-II Pro FPGA family presently has five membersÑXC2VP2, -4, -7, -20 and -50Ñeach varying as to the number of logic cells (3,168 to 50,832), RocketIO blocks (4 to 16), PowerPC cores (0 to 4), Block RAM (216 to 3,888 Kb), DCM blocks (4 to 8), and multipliers (16 to 264) it contains. The XC2VP7, -20 and -50 are available now, with the XC2VP7, a 11,088-logic cell, 8-RocketIO block, 1-PowerPC core, 792-Kb Block RAM, 4-DCM block, 60-multiplier device, costing $120 each/25K. The XC2VP2 and -4 parts are expected to become available in mid-2002. For more details, contact Rob Schreck at XILINX INC., San Jose, CA. (408) 879-6701.
Company - XILINX
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