FIFO Family Members Integrate DDR Capabilities March 2002 Issue Published Date: March 01, 2002
The industryÕs first FIFO products to offer double data rate (DDR) capabilities are said to be now available in the form of the recently launched TeraSync family. The DDR FIFOs more than double the bandwidth currently available for leading-edge applications in enterprise and carrier class markets. The devices feature clock cycle speeds up to 250 MHz and per-pin data rates up to 500 Mbps. In addition, with a 40-bit wide data bus, the DDR FIFOÕs interface can handle 20 Gbps of data throughput, supporting applications in SONET, fibre channel and gigabit Ethernet, as well as image processing and instrumentation. The TeraSync DDR FIFOs have a number of other advanced features, such as double to single data rate matching and an echo clock and echo enable on the read port. And user-selectable I/Os support 2.5V LVTTL/LVCMOS with 3.3V tolerant inputs, 1.8V LVCMOS/eHSTL, and 1.5V HSTL. Besides these features, the FIFO family is also said to have extremely low power dissipation. And two of the DDR FIFOs can be used in parallel to reportedly allow applications to implement OC-768 line-rate buffering in an efficient manner. Available in a 208-pin BGA package and in x10, x20 and x40 configurations, the TeraSync DDR FIFOs carry a starting price tag of less than $38 each/10K. INTEGRATED DEVICE TECHNOLOGY INC., Santa Clara, CA. (800) 345-7015.
