Packet Processor Supports Full-Duplex 20-Gbps Data Rates November 2001 Issue Published Date: November 01, 2001
Capable of supporting Layer 2-7 switching and routing of up to 20 full-duplex Gigabit Ethernet ports simultaneously, the iFlow Packet Processor (iPP) is a high-performance, 20-Gbps, multi-threaded, wire-speed IC boasting of a top processing speed of 30 million packets per second. Part of the iFlow Data Path Processing Platform (DP3) family of products, the new packet processor also provides high-touch capabilities at wire rate for both Ethernet and Packet-over-SONET systems. And it can deliver over 115 Gbps of external interface bandwidth for connecting to look-aside or in-line coprocessors and supports hot software upgrades and hot-pluggable I/O for interface hardware upgrades. Running at speeds of up to 333 MHz, the iPP is made using a 0.13-micron, 1.2V CMOS process and numbers among its 125 million on-chip transistors circuitry for: 32 multi-threaded packet processors; 1K x 72 bits of ternary CAM; 4 Mb of scratch pad memory; packet buffering RAM; two receive and two transmit SPI4.2 interfaces; a 32-bit, 33- or 66-MHz PCI 2.2 control plane interface; and LVDS high-speed coprocessor channels with 6.4-Gbps bandwidth in each direction. The iFlow Packet Processor comes in a 1,170-ball HPBGA package, is priced as low as $1,000 each in high volumes, and will begin shipping in Q1 2002. For more details, contact Mitch Kahn at SILICON ACCESS NETWORKS INC., San Jose, CA. (408) 545-1100.
