IP Core Integrates Easily Into SOC Designs May 2000 Issue Published Date: May 01, 2000
Designed for easy integration into system-on-chip (SOC) designs, the BK-3709 IDE Host Controller IP core provides a complete IDE host controller subsystem. Using the core, system OEMs and fabless semiconductor companies can develop complete IDE host controller solutions faster and with lower development costs, it's claimed. The controller includes all of the digital circuitry needed to provide a complete interface between a host processor system and an IDE- or ATAPI-compatible hard drive subsystem or device. It includes programmed I/O, multi-word direct memory access, and Ultra ATA interface circuitry. It supports up to four separate hard disk drive devices. The core supports primary and secondary data channels with independent or combined interrupts. It supports PIO models 1 through 4, multi-word DMA modes 0, 1 and 2, and synchronous Ultra ATA-33 and ATA-66 modes 0 through 4. The design is verified for operation at clock speeds of up to 100 MHz. The core is shipped as RTL Verilog source code. Documentation, synthesis scripts, and a test bench are available. The test bench includes the RTL source code, a simulation harness, models for the ATA slave devices, DMA and control interfaces, and test stimulus files. Call for pricing.
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