New PLL Family Says Its Phase Noise Is The Lowest April 2000 Issue Published Date: April 01, 2000
Clearer voice and higher data throughput transmissions are claimed for RF products and systems using a member of a new family of radio frequency phase lock loop (RF PLL) devices. Targeted at communication systems, such as broadband networks, RF base stations, wireless local loops, and cell phones, the CYW23xx family consists of three single PLL and six dual PLL ICs that support frequency outputs of from 0.5 to 2.5 GHz. The devices are said to offer the industry's lowest phase noise floor while maintaining footprint- and register-compatibility with National Semiconductor's LMX23xx series of PLLatinum PLLs-- e.g., the 2.0-GHz CYW2336's phase noise is reportedly 3 dB lower than National's LMX2336 RF PLL. Made using a 0.25-µm BiCMOS process, the CYW23xx PLLs are 3.3V devices housed in 20-pin TSSOPs costing $2 to $3.50 each.
