Layer-2 Switch, Transceivers & Memory Integrated Onto Single IC April 2000 Issue Published Date: April 01, 2000
By melding together SRAM, five PHY transceivers, five Media Access Control (MAC) units and a layer-2 switch, the KS8995 achieves with one IC what previously required two or three different chips. The new IC runs in two modes: a five-port integrated switch mode and a five-port switch mode in which the fifth port is decoupled from the PHY and the fifth MAC is accessed via a reverse Media Independent Interface (MII) or 7-wire interface. This enables interfacing to public networks via a network processor. The KS8995 chip also includes: hardware-based 10/100, full- or half-duplex, flow control and auto negotiation; individual port-forced modes (full duplex, 100BaseTX) when auto negotiation is disabled; full-duplex IEEE 802.3x flow control; half-duplex back pressure flow control; wire speed reception and transmission; and unmanaged operation through strapping at system reset time. Other elements of the 5-port 10/100 switch with PHY include: an integrated address look-up engine that supports 1K absolute MAC address; automatic address learning, aging and migration; broadcast storm protection; LED support; and indicators for link, activity, full/half-duplex and speed. Applications for the IC include 100BaseTX, 100BaseFX and 10BaseT SOHO LANs, with physical signal transmission and reception for these applications enhanced through the use of analog circuitry that is said to make the design more efficient and to allow for lower power consumption and smaller chip size. The mixed-signal architecture device requires only a single 2.5V supply, dissipates 1.25W (includes physical transmit drivers), and comes in 128-pin PQFPs costing $20 each/1000.
